This invention relates to a semiconductor memory system, and more particularly to a semiconductor memory system which allows a dynamic random access.
Of MOS type semiconductor memories, the dRAM (dynamic random access memory) has increased its capacity at the rate of 400% every 3 years. A dRAM with the capacity of 1M bits has already been put to practical use. At the ISSCC (International Solid State Circuit Conference) held in 1986, several dRAMs having the capacity of 4M bits were presented.
With the increase of the memory capacity of the dRAM, great improvements have been made in the functions of the memory system, for example, use of a multi-bit system for the input/output and diversification of the operation modes. Particularly, in the page mode, nibble mode and static column mode, a high speed read/write operation is possible for a plurality of memory cells connected to a selected word line. Therefore, in these modes, the dRAM system can make a high speed access as fast as the static RAM system. In such high-speed operation modes, the performance of a computer can be improved, since the data can be input or output serially. If such a memory system is applied to an image memory, the picture quality can be improved.
In a computer system, to improve the data transfer speed between a main memory unit and a central processing unit (CPU), a cache memory is frequently located between these units and the data transfer is performed every fixed length data block. Also, to increase the throughput of the memory, the memory card groups constituting the main memory are arranged into memory banks. The addresses are successively allotted to these memory banks. The data in these memory banks are processed in parallel (the interleaving system). In this way, the mean memory cycle time is reduced. At present, the nibble mode is often used as an operation mode for realizing the reduction of the cycle time. In the nibble mode, a row address strobe signal (referred to as an RAS clock) is pulsed from "1" (H) level to "0" (L) level, so that the memory cells are activated. Then, the column address strobe signal (referred to as a CAS clock) is pulsed from "H" to "L", and one memory cell is selected. Subsequently, the CAS clock is reset and rendered "L" again while the RAS clock is kept at "L". This cyclic operation in which the CAS clock is reset and rendered "L" again is called a toggle of the CAS clock. This cyclic operation is repeated, so that column addresses are successively accessed without any supply of the column address signals from outside.
The operation of the prior art in the nibble mode will be described, referring to FIGS. 1 and 2. When the RAS clock is pulsed from "H" to "L", a train of activate signals are generated. First, row address signals are supplied to ten row address buffers (ten buffers for in a 1M bit dRAM and eleven for a 4M bit dRAM). A row address binary code in a MOS level is produced by each of the row address buffers. The row address binary codes produced by the row address buffers are transferred to row decoders, to execute select or non-select of row decoders. As a result of detecting the select or non-select of row decoders, a word line drive clock is generated. A word line WL which is provided corresponding to the word line drive clock is then selected. Data in memory cells M1, M2, M3 and M4 which are connected to the selected word line WL are transferred to the associated bit lines. The transferred data are amplified by respective bit line sense amplifiers SA1 to SA4. Next, the CAS clock is input, and column address signals are supplied to the ten column address buffers. Column address binary codes A0c to Anc in the MOS level are produced by column address buffers. Of these column address binary codes, eight codes are used for the select or the non-select of the column decoders. The remaining two codes are supplied to a decoder for selecting four input/output lines (I/O lines) DQ.sub.1 to DQ.sub.4. For example, the 256 column decoders (N=1 to 256) receive eight column address binary codes (A0c - Anc: n=8), and one column decoder (N) is selected. The selected column decoder N causes column select signal CSL to rise. Then, transfer gates or column select gates Q.sub.801 to Q.sub.804 are turned on. The data of four pairs of bit lines are respectively transferred to four pairs of I/O lines DQ.sub.1 to DQ.sub.4. In FIG. 1, the bit line pair is simplified by illustrating it as one line. The data transferred to I/O lines DQ.sub.1 to DQ.sub.4 are amplified by four output data amplifiers S1 to S4 which are activated by control signal QSE. Data readout gates Q.sub.805 to Q.sub.808 which are controlled by control signal QSE simultaneously with the signal amplification, are turned on. The data on I/O lines DQ.sub.1 to DQ.sub.4 are transferred to data output lines RD.sub.1 to RD.sub.4. The data on data output lines RD.sub.1 to RD.sub.4 are stored in output data latch circuits L1 to L4, each made up of a flip-flop. The stored data are converted from parallel to serial form by an output data shift register. Output data Dout is serially output from the data output terminal when data output data buffer is activated. A pointer control means is included in the output data shift register for deciding which data from data latch circuits L1 to L4 should be output first. Write data Din (or input data) input from an input data input terminal (not shown) via input data buffer, are transferred to an input data shift register. The data are sequentially supplied to input data latch circuits L1' to L4', in synchronism with the toggles of the CAS clock. When the input data are supplied to latch circuits L1' to L4', write gates Q.sub.809 to Q.sub.812 are kept turned on by write control signals WG.
As prior dRAMs, those with shift register lengths of 4 bits, 8 bits and 1024 bits have been used for the shift register length in the nibble mode. The operation of dRAM when the 4-bit length shift register is used usually in the nibble mode. The timing diagram illustrating the nibble mode operation is shown in FIG. 3. The operation mode when the 8-bit length shift register is used is called a bite mode, and may be illustrated as shown in FIG. 4. The operation mode when the 1024-bit length shift register is used is called an extended nibble mode, and operates as shown in FIG. 5. The bit length for the extended nibble mode differs with the length of the column of the memory cell array. It can take the values of 512 bits, 2,048 bits or 4,096 bits, for example.
In the read/write operations in this nibble mode, data can be input and output at a higher speed than in the normal mode of the prior art. When data are sequentially read out in the normal cycle, it is necessary, as shown in FIG. 6, to first return both RAS clock and CAS clock in logical state from "L" to "H", i.e., to return the clocks to a precharge state, and then to input row address signal Xi and column address signal Yi which are for addressing a desired memory location. Presence of the precharge period elongates the read/write cycle time.
The nibble mode, bite mode, and the extended nibble mode involve the following problem as to the high-speed operation. In the nibble mode of the prior art, the shift register has a 4 bit length. The data of 4 serial bits can be read and written in synchronism with the toggles of the CAS clock. As shown in FIG. 7, however, when data of 5 or more serial bits are processed, for example, read out, the output data R1 to R4 of 4 bits are first read out, and then precharge is performed, to return RAS clock and CAS clock to "H" level. Next, through the RAS/CAS cycle, the operation for reading out the next 4-bit output data R5 to R8, is necessary. Therefore, it is evident that the mean cycle time is longer than the toggle of the CAS clock. The bite mode also involves the same problem as that of FIG. 7, as shown in FIG. 8 when the 9 or more successive bit output data is read out. The same thing is true for the data write operation. In the extended nibble mode of the prior art, data can be sequentially read and written through the mean cycle time approximately equal to the cycle time of the toggle of the CAS clock. However, to realize this extended nibble mode, 1,024 shift registers are required. Also, the number of I/O lines for transferring the outputs of sense amplifiers to the data output buffers, and for transferring the data from the data input buffer to the memory cells, must be increased. As a result, the chip area increases, and so does the manufacturing cost.